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HB52F648EN-75B, HB52F649EN-75B
512 MB Unbuffered SDRAM DIMM, 133 MHz Memory Bus (HB52F648EN) 64-Mword x 64-bit, 2-Bank Module (16 pcs of 32 M x 8 Components) (HB52F649EN) 64-Mword x 72-bit, 2-Bank Module (18 pcs of 32 M x 8 Components) PC133 SDRAM
E0012H10 (1st edition) (Previous ADE-203-1115A (Z)) Preliminary Jan. 17, 2001 Description
The HB52F648EN, HB52F649EN belong to 8-byte DIMM (Dual In-line Memory Module) family, and have been developed as an optimized main memory solution for 8-byte processor applications. They are synchronous Dynamic RAM Module, mounted 256-Mbit SDRAMs (HM5225805BTT) sealed in TSOP package, and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). The HB52F648EN is organized 32M x 64 x 2-bank mounted 16 pieces of 256-Mbit SDRAM. The HB52F649EN is organized 32M x 72x 2-bank mounted 18 pieces of 256-Mbit SDRAM. An outline of the products is 168-pin socket type package (dual lead out). Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* Fully compatible with : JEDEC standard outline 8-byte DIMM * 168-pin socket type package (dual lead out) Outline: 133.37 mm (Length) x 34.925 mm (Height) x 4.00 mm (Thickness) Lead pitch: 1.27 mm * 3.3 V power supply * Clock frequency: 133 MHz (max) * LVTTL interface
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Elpida Memory, Inc. regarding specification. Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52F648EN/HB52F649EN-75B
* Data bus width : x 64 Non parity (HB52F648EN) : x 72 ECC (HB52F649EN) * Single pulsed RAS * 4 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length: 1/2/4/8 * 2 variations of burst sequence Sequential Interleave * Programmable CE latency : 3 (133 MHz) : 2 (100 MHz) * Byte control by DQMB * Refresh cycles: 8192 refresh cycles/64 ms * 2 variations of refresh Auto refresh Self refresh
Ordering Information
Type No.
1 1
Frequency
CE latency 3 3
Package 168-pin dual lead out socket type
Contact pad Gold
HB52F648EN-75B* 133 MHz HB52F649EN-75B* 133 MHz Note:
1. 100 MHz operation at CE latency = 2.
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
Preliminary Data Sheet E0012H10 2
HB52F648EN/HB52F649EN-75B
(HB52F648EN)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC NC VSS NC NC VCC W DQMB0 DQMB1 S0 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin name VSS NC S2 DQMB2 DQMB3 NC VCC NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC (CKE1)*1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 Pin name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC NC VSS NC NC VCC CE DQMB4 DQMB5 NC (S1)*
3
Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
Pin name VSS CKE0 NC (S3)*2 DQMB6 DQMB7 NC VCC NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59
Preliminary Data Sheet E0012H10 3
HB52F648EN/HB52F649EN-75B
Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 Pin name NC VSS A0 A2 A4 A6 A8 A10 (AP) BA1 VCC VCC CK0 Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 Pin name VCC DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VCC Pin No. 115 116 117 118 119 120 121 122 123 124 125 126 Pin name RE VSS A1 A3 A5 A7 A9 BA0 A11 VCC CK1 A12 Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 Pin name VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VCC
Notes: 1. CKE1: HB52F648EN 2. S3: HB52F648EN 3. S1: HB52F648EN
Preliminary Data Sheet E0012H10 4
HB52F648EN/HB52F649EN-75B
(HB52F649EN)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC W DQMB0 DQMB1 S0 NC VSS A0 A2 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Pin name VSS NC S2 DQMB2 DQMB3 NC VCC NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC
1
Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
Pin name VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC CE DQMB4 DQMB5 NC (S1)* RE VSS A1 A3
3
Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Pin name VSS CKE0 NC (S3)*2 DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62
NC (CKE1)* 105 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 106 107 108 109 110 111 112 113 114 115 116 117 118
Preliminary Data Sheet E0012H10 5
HB52F648EN/HB52F649EN-75B
Pin No. 35 36 37 38 39 40 41 42 Pin name A4 A6 A8 A10 (AP) BA1 VCC VCC CK0 Pin No. 77 78 79 80 81 82 83 84 Pin name DQ31 VSS CK2 NC WP SDA SCL VCC Pin No. 119 120 121 122 123 124 125 126 Pin name A5 A7 A9 BA0 A11 VCC CK1 A12 Pin No. 161 162 163 164 165 166 167 168 Pin name DQ63 VSS CK3 NC SA0 SA1 SA2 VCC
Notes: 1. CKE1: HB52F649EN 2. S3: HB52F649EN 3. S1: HB52F649EN
Pin Description (HB52F648EN)
Pin name A0 to A12 Function Address input Row address A0 to A12 Column address A0 to A9 BA0/BA1 DQ0 to DQ63 S0 to S3 RE CE W DQMB0 to DQMB7 CK0 to CK3 CKE0, CKE1 WP SDA SCL SA0 to SA2 VCC VSS NC Bank select address Data input/output Chip select input Row enable (RAS) input Column enable (CAS) input Write enable input Byte data mask Clock input Clock enable input Write protect for serial PD Data input/output for serial PD Clock input for serial PD Serial address input Primary positive power supply Ground No connection
Preliminary Data Sheet E0012H10 6
HB52F648EN/HB52F649EN-75B
Pin Description (HB52F649EN)
Pin name A0 to A12 Function Address input Row address A0 to A12 Column address A0 to A9 BA0/BA1 DQ0 to DQ63 CB0 to CB7 S0 to S3 RE CE W DQMB0 to DQMB7 CK0 to CK3 CKE0, CKE1 WP SDA SCL SA0 to SA2 VCC VSS NC Bank select address Data input/output Check bit (Data input/output) Chip select input Row enable (RAS) input Column enable (CAS) input Write enable input Byte data mask Clock input Clock enable input Write protect for serial PD Data input/output for serial PD Clock input for serial PD Serial address input Primary positive power supply Ground No connection
Preliminary Data Sheet E0012H10 7
HB52F648EN/HB52F649EN-75B
Serial PD Matrix*1
Byte No. Function described 0 1 2 3 4 5 6 Number of bytes used by module manufacturer Total SPD memory size Memory type Number of row addresses bits Number of column addresses bits Number of banks Module data width (HB52F648EN) (HB52F649EN) 7 8 9 Module data width (continued) Module int erf ac e signal lev els SDRAM cycle time (highest CE latency) 7.5 ns SDRAM access from Clock (highest CE latency) 5.4 ns Module configuration type (HB52F648EN) (HB52F649EN) 12 Refresh rate/type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 80 08 04 0D 0A 02 40 48 00 01 75 128 256 byte SDRAM 13 10 2 64 72 0 (+) LVTTL CL = 3
10
0
1
0
1
0
1
0
0
54
11
0 0 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 1 1
0 0 0
00 02 82
Non parity ECC Normal (7.8125 s) Self refresh 32M x 8 -- x8 1 CLK
13 14
SDRAM width
0
0 0 0 0
0 0 0 0
0 0 0 0
1 0 1 0
0 0 0 0
0 0 0 0
0 0 0 1
08 00 08 01
Error checking SDRAM width (HB52F648EN) 0 (HB52F649EN) 0 0
15
SDRAM device attributes: minimum clock delay for back-to-back random column addresses SDRAM device attributes: Burst lengths supported
16
0
0
0
0
1
1
1
1
0F
1, 2, 4, 8
Preliminary Data Sheet E0012H10 8
HB52F648EN/HB52F649EN-75B
Byte No. Function described 17 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 1 0 0 04 4 SDRAM device attributes: 0 number of banks on SDRAM device SDRAM device attributes: CE latency SDRAM device attributes: S latency SDRAM device attributes: W latency SDRAM module attributes SDRAM device attributes: General SDRAM cycle time (2nd highest CE latency) 10 ns SDRAM access from Clock (2nd highest CE latency) 6 ns SDRAM cycle time (3rd highest CE latency) Undefined SDRAM access from Clock (3rd highest CE latency) Undefined 0 0 0 0 0 1
18 19 20 21 22 23
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 0 0
0 0 0 0 1 0
1 0 0 0 1 0
1 0 0 0 1 0
0 1 1 0 0 0
06 01 01 00 0E A0
2, 3 0 0 Non buffer VCC 10% CL = 2
24
0
1
1
0
0
0
0
0
60
25
0
0
0
0
0
0
0
0
00
26
0
0
0
0
0
0
0
0
00
27 28 29 30 31 32 33 34 35
Minimum row precharge time 0 Row active to row active min 0 RE to CE delay min Minimum RE pulse width Density of each bank on module Address and command signal input setup time Address and command signal input hold time 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0
1 0 1 0 0 1 0 1 0 0 0
0 1 0 1 0 0 1 0 1 0 0
1 1 1 1 0 1 0 1 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 1 0 1 0 1 0 1 0 0 0
14 0F 14 2D 40 15 08 15 08 00 02
20 ns 15 ns 20 ns 45 ns 2 bank 256 M byte 1.5 ns 0.8 ns 1.5 ns 0.8 ns Future use JEDEC2
Data signal input setup time 0 Data signal input hold time 0 0 0
36 to 61 Superset information 62 SPD data revision code
Preliminary Data Sheet E0012H10 9
HB52F648EN/HB52F649EN-75B
Byte No. Function described 63 Checksum for bytes 0 to 62 (HB52F648EN) (HB52F649EN) 64 Manuf ac t urer's JEDEC ID c ode Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 x 1 1 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 x 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 1 1 1 1 0 1 0 0 x 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 x 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 x 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 0 1 0 x 0 1 0 1 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 1 0 x 0 0 1 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 43 55 07 00 xx 48 42 35 32 46 36 34 38 39 45 4E 2D 37 35 42 20 20 20 20 * 2 (ASCII8bit code) H B 5 2 F 6 4 8 9 E N -- 7 5 B (Space) (Space) (Space) (Space) 67 85 HITACHI
65 to 71 Manuf ac t urer's JEDEC ID c ode 72 73 74 75 76 77 78 79 80 Manufacturing location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (HB52F648EN) (HB52F649EN) 81 82 83 84 85 86 87 88 89 90 Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number
Preliminary Data Sheet E0012H10 10
HB52F648EN/HB52F649EN-75B
Byte No. Function described 91 92 93 94 Revision code Revision code Manufacturing date Manufacturing date Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 x x *3 -- -- 1 1 -- 1 1 -- 0 1 -- 0 1 -- 1 1 -- 0 1 -- 0 1 -- 64 FF *4 0 0 x x 1 1 x x 1 0 x x 0 0 x x 0 0 x x 0 0 x x 0 0 x x 30 20 xx xx Initial (Space) Year code (BCD) Week code (BCD)
95 to 98 Assembly serial number 99 to 125 Manufacturer specific data 126 127
Reserved (Intel specification 0 frequency) Reserved (Intel specification 1 CE# latency support)
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 125 are not defined ("1" or "0").
Preliminary Data Sheet E0012H10 11
HB52F648EN/HB52F649EN-75B
Block Diagram (HB52F648EN)
A0 to A12, BA0, BA1 RE, CE, W S1 S0 CS DQMB0 DQ0 to DQ7 8 10 DQM I/O0 to I/O7 CS DQM 8 10 I/O0 to I/O7 CS CS CS
D0
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D8
DQMB4 8 DQ32 to DQ39 10
DQM I/O0 to I/O7 CS DQM 10 I/O0 to I/O7
D4
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D12
DQMB1 DQ8 to DQ15
D1
D9
DQMB5 8 DQ40 to DQ47
D5
D13
S3 S2 CS DQMB2 DQ16 to DQ23 8 10 DQM I/O0 to I/O7 CS DQM 8 10 I/O0 to I/O7 CS CS CS
D2
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D10
DQMB6 8 DQ48 to DQ55 10
DQM I/O0 to I/O7 CS DQM 10 I/O0 to I/O7
D6
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D14
DQMB3 DQ24 to DQ31
D3
D11
DQMB7 8 DQ56 to DQ63
D7
D15
10 CK0 10 CK1 10 CK2 10 CK3
VCC 0.33 F CLK; 4 SDRAMs + 3.3 pF cap x 16 pcs VSS CLK; 4 SDRAMs + 3.3 pF cap CKE0
VCC (D0 to D15, U0) 0.1 F x 16 pcs VSS (D0 to D15, U0) CKE (D0 to D7)
CLK; 4 SDRAMs + 3.3 pF cap CKE1 CLK; 4 SDRAMs + 3.3 pF cap SCL
10 k CKE (D8 to D15) Serial PD SCL SDA SDA WP 47 k SA0 SA1 SA2 VSS Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D15: HM5225805 U0: 2-kbit EEPROM
U0
A0 A1 A2
Preliminary Data Sheet E0012H10 12
HB52F648EN/HB52F649EN-75B
Block Diagram (HB52F649EN)
A0 to A12, BA0, BA1 RE, CE, W S1 S0 CS DQMB0 DQ0 to DQ7 8 10 DQM I/O0 to I/O7 CS DQM 8 10 I/O0 to I/O7 CS DQM CB0 to CB7 S3 S2 CS DQMB2 DQ16 to DQ23 8 10 DQM I/O0 to I/O7 CS DQM 8 10 I/O0 to I/O7 CS CS CS 8 10 I/O0 to I/O7 CS CS CS
D0
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7 CS
D9
DQMB4 8 DQ32 to DQ39 10
DQM I/O0 to I/O7 CS DQM 10 I/O0 to I/O7
D5
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D14
DQMB1 DQ8 to DQ15
D1
D10
DQMB5 8 DQ40 to DQ47
D6
D15
DQM
D2
I/O0 to I/O7
D11
D3
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D12
DQMB6 8 DQ48 to DQ55 10
DQM I/O0 to I/O7 CS DQM 10 I/O0 to I/O7
D7
DQM I/O0 to I/O7 CS DQM I/O0 to I/O7
D16
DQMB3 DQ24 to DQ31
D4
D13
DQMB7 8 DQ56 to DQ63 VCC
D8
D17
10 CK0 10 CK1 10 CK2 10 CK3 CLK (4 SDRAMs + 3.3 pF cap) CLK (4 SDRAMs + 3.3 pF cap) CLK (5 SDRAMs) CLK (5 SDRAMs)
VCC (D0 to D17, U0) 0.1 F x 18 pcs VSS (D0 to D17, U0) CKE (D0 to D8) VCC 10 k
0.33 F x 18 pcs VSS CKE0
CKE1 Serial PD SCL SCL SDA
CKE (D9 to D17)
SDA WP 47 k
U0
A0 A1 A2
VSS SA0 SA1 SA2 Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D17: HM5225805 U0: 2-kbit EEPROM
Preliminary Data Sheet E0012H10 13
HB52F648EN/HB52F649EN-75B
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation (HB52F648EN) Power dissipation (HB52F649EN) Operating temperature Storage temperature Note: 1. Respect to V SS Symbol VT VCC Iout PT PT Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 8.0 9.0 0 to +65 -55 to +125 Unit V V mA W W C C Note 1 1
DC Operating Conditions (Ta = 0 to +65C)
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Notes: 1. 2. 3. 4. 5. VIH VIL Min 3.0 0 2.0 -0.3 Max 3.6 0 VCC + 0.3 0.8 Unit V V V V Notes 1, 2 3 1, 4 1, 5
All voltage referred to VSS The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max) = VCC + 2.0 V for pulth width 3 ns at VCC. VIL (min) = VSS - 2.0 V for pulth width 3 ns at VSS .
Preliminary Data Sheet E0012H10 14
HB52F648EN/HB52F649EN-75B
VIL/VIH Clamp (Component characteristic)
This SDRAM component has VIL and V IH clamp for CK, CKE, S, DQMB and DQ pins. Minimum VIL Clamp Current
VIL (V) -2 -1.8 -1.6 -1.4 -1.2 -1 -0.9 -0.8 -0.6 -0.4 -0.2 0 I (mA) -32 -25 -19 -13 -8 -4 -2 -0.6 0 0 0 0
0 -5 -10 I (mA) -15 -20 -25 -30 -35
-2
-1.5
-1
-0.5
0
VIL (V)
Preliminary Data Sheet E0012H10 15
HB52F648EN/HB52F649EN-75B
Minimum VIH Clamp Current
VIH (V) VCC + 2 VCC + 1.8 VCC + 1.6 VCC + 1.4 VCC + 1.2 VCC + 1 VCC + 0.8 VCC + 0.6 VCC + 0.4 VCC + 0.2 VCC + 0 I (mA) 10 8 5.5 3.5 1.5 0.3 0 0 0 0 0
10 8 I (mA) 6 4 2 0 VCC + 0 VCC + 0.5 VCC + 1 VIH (V) VCC + 1.5 VCC + 2
Preliminary Data Sheet E0012H10 16
HB52F648EN/HB52F649EN-75B
IOL/IOH Characteristics (Component characteristic)
Output Low Current (IOL)
I OL Vout (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 Min (mA) 0 27 41 51 58 70 72 75 77 77 80 81 I OL Max (mA) 0 71 108 134 151 188 194 203 209 212 220 223
250
200 IOL (mA)
150 min max 100
50
0 0 0.5 1 1.5 2 Vout (V) 2.5 3 3.5
Preliminary Data Sheet E0012H10 17
HB52F648EN/HB52F649EN-75B
Output High Current (I OH ) (Ta = 0 to 65C, V CC = 3.0 V to 3.45 V, VSS = 0 V)
I OH Vout (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1.4 1 0 Min (mA) -- -- 0 -21 -34 -59 -67 -73 -78 -81 -89 -93 I OH Max (mA) -3 -28 -75 -130 -154 -197 -227 -248 -270 -285 -345 -503
0
0
0.5
1
1.5
2
2.5
3
3.5
-100
IOH (mA)
-200 min -300 max
-400
-500
-600 Vout (V)
Preliminary Data Sheet E0012H10 18
HB52F648EN/HB52F649EN-75B
DC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HB52F648EN)
HB52F648EN-75B PC133 CE latency = 3 Parameter Operating current Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Active standby current in power down Active standby current in non power down Burst operating current Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage Symbol Min I CC1 I CC2P I CC2PS -- -- -- Max 1120 48 32 PC100 CE latency = 2 Min -- -- -- Max 1120 48 32 Unit Test conditions mA Burst length = 1 t RC = min Notes 1, 2, 3
mA CKE = VIL, t CK = 12 ns 6 mA CKE = VIL, t CK = 7
I CC2N I CC3P I CC3N I CC4 I CC5 I CC6 I LI I LO VOH VOL
-- -- -- -- -- -- -10 -10 2.4 --
320 64 480 1320 2000 48 10 10 -- 0.4
-- -- -- -- -- -- -10 -10 2.4 --
320 64 480 1040 2000 48 10 10 -- 0.4
mA CKE, S = VIH, t CK = 12 ns
4
mA CKE = VIL, t CK = 12 ns 1, 2, 6 mA CKE, S = VIH, t CK = 12 ns mA t CK = min, BL = 4 mA t RC = min mA VIH VCC - 0.2 V VIL 0.2 V A A V V 0 Vin VCC 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA 1, 2, 4 1, 2, 5 3 8
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK operating current. 7. After power down mode, no CK operating current. 8. After self refresh mode set, self refresh current.
Preliminary Data Sheet E0012H10 19
HB52F648EN/HB52F649EN-75B
DC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HB52F649EN)
HB52F649EN-75B PC133 CE latency = 3 Parameter Operating current Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Active standby current in power down Active standby current in non power down Burst operating current Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage Symbol Min I CC1 I CC2P I CC2PS -- -- -- Max 1260 54 36 PC100 CE latency = 2 Min -- -- -- Max 1260 54 36 Unit Test conditions mA Burst length = 1 t RC = min Notes 1, 2, 3
mA CKE = VIL, t CK = 12 ns 6 mA CKE = VIL, t CK = 7
I CC2N I CC3P I CC3N I CC4 I CC5 I CC6 I LI I LO VOH VOL
-- -- -- -- -- -- -10 -10 2.4 --
360 72 540 1485 2250 54 10 10 -- 0.4
-- -- -- -- -- -- -10 -10 2.4 --
360 72 540 1170 2250 54 10 10 -- 0.4
mA CKE, S = VIH, t CK = 12 ns
4
mA CKE = VIL, t CK = 12 ns 1, 2, 6 mA CKE, S = VIH, t CK = 12 ns mA t CK = min, BL = 4 mA t RC = min mA VIH VCC - 0.2 V VIL 0.2 V A A V V 0 Vin VCC 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA 1, 2, 4 1, 2, 5 3 8
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CK operating current. 7. After power down mode, no CK operating current. 8. After self refresh mode set, self refresh current.
Preliminary Data Sheet E0012H10 20
HB52F648EN/HB52F649EN-75B
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V) (HB52F648EN)
Parameter Input capacitance (Address) Input capacitance (RE, CE, W) Input capacitance (CKE) Input capacitance (S) Input capacitance (CK) Input capacitance (DQMB) Input/Output capacitance (DQ) Notes: 1. 2. 3. 4. Symbol CI1 CI2 CI3 CI4 CI5 CI6 CI/O1 Max 105 90 68 38 50 23 22 Unit pF pF pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested.
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V) (HB52F649EN)
Parameter Input capacitance (Address) Input capacitance (RE, CE, W) Input capacitance (CKE) Input capacitance (S) Input capacitance (CK) Input capacitance (DQMB) Input/Output capacitance (DQ) Notes: 1. 2. 3. 4. Symbol CI1 CI2 CI3 CI4 CI5 CI6 CI/O1 Max 112 97 70 40 50 27 22 Unit pF pF pF pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Data-out. This parameter is sampled and not 100% tested.
Preliminary Data Sheet E0012H10 21
HB52F648EN/HB52F649EN-75B
AC Characteristics (Ta = 0 to 65C, VCC = 3.3 V 0.3 V, VSS = 0 V)
HB52F648EN/649EN-75B PC133 CE latency = 3 Parameter System clock cycle time CK high pulse width CK low pulse width Access time from CK Data-out hold time CK to Data-out low impedance CK to Data-out high impedance Data-in setup time Data in hold time Address setup time Address hold time CKE setup time PC100 Symbol Symbol Min t CK t CKH t CKL t AC t OH t LZ t HZ t DS t DH t AS t AH t CES Tsi Thi Tsi Thi Tsi Tpde Thi Tsi Thi Trc Tras Trcd Trp Tdpl Trrd Tclk Tch Tcl Tac Toh 7.5 2.5 2.5 -- 2.7 2 -- 1.5 0.8 1.5 0.8 1.5 1.5 0.8 1.5 0.8 67.5 45 20 20 15 15 1 -- Max -- -- -- 5.4 -- -- 5.4 -- -- -- -- -- -- -- -- -- -- PC100 CE latency = 2 Min 10 3 3 -- 3 2 -- 2 1 2 1 2 2 1 2 1 70 Max -- -- -- 6 -- -- 6 -- -- -- -- -- -- -- -- -- -- 120000 -- -- -- -- 5 64 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 1 1 1 1, 2 1, 2 1, 2, 3 1, 4 1 1 1 1 1, 5 1 1 1 1 1 1 1 1 1 1
CKE setup time for power down exit t CESP CKE hold time Command setup time Command hold time Ref/Active to Ref/Active command period Active to precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period t CEH t CS t CH t RC t RAS t RCD t RP t DPL t RRD tT t REF
120000 50 -- -- -- -- 5 64 20 20 20 20 1 --
Preliminary Data Sheet E0012H10 22
HB52F648EN/HB52F649EN-75B
Notes: 1. 2. 3. 4. 5. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is C L = 50 pF. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions * Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures
2.4 V
input
0.4 V
2.0 V 0.8 V
DQ CL t
T
tT
Preliminary Data Sheet E0012H10 23
HB52F648EN/HB52F649EN-75B
Relationship Between Frequency and Minimum Latency
Parameter HB52F648EN/649EN-75B 133 Frequency (MHz) tCK (ns) Active command to column command (same bank) Active command to active command (same bank) CE latency = 3 PC100 Symbol Symbol 7.5 I RCD I RC 3 9 6 3 Tdpl 2 2 Tsrx Tdal 1 5 9 Troh 3 1 -2 Tccd Tdwd Tdqm Tdqz Tcke Tmrd 1 0 0 2 1 1 0 1 100 CE latency = 2 10 2 7 5 2 2 2 1 4 7 2 1 -1 1 0 0 2 1 1 0 1 Notes 1 = [IRAS + IRP] 1 1 1 1 1 2 = [IDPL + IRP] = [IRC] 3
Active command to precharge command I RAS (same bank) Precharge command to active command I RP (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) Column command to column command Write command to data in latency DQMB to data in DQMB to data out CKE to CK disable Register set to active command S to command disable Power down exit to command input I DPL I RRD I SREX I APW I SEC I HZP I APR I EP I CCD I WCD I DID I DOD I CLE I RSA I CDD I PEC
Preliminary Data Sheet E0012H10 24
HB52F648EN/HB52F649EN-75B
Notes: 1. I RCD to IRRD are recommended value. 2. Be valid [DSEL] or [NOP] at next command of self refresh exit. 3. Except [DSEL] and [NOP]
Pin Functions
CK0 to CK3 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. S0 to S3 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1 (BS) is precharged. BA0/BA1 (input pin): BA0/BA1 are bank select signal (BS). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 is Low and BA0 is Low, bank 0 is selected. If BA1 is High and BA0 is Low, bank 1 is selected. If BA1 is Low and BA0 is High, bank 2 is selected. If BA1 is High and BA0 is High, bank 3 is selected. CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63 (input/output pins): Data is input to and output from these pins. CB0 to CB7 (input/output pins): Data is input to and output from these pins. VCC (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected.
Preliminary Data Sheet E0012H10 25
HB52F648EN/HB52F649EN-75B
Detailed Operation Part
Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet.
Preliminary Data Sheet E0012H10 26
HB52F648EN/HB52F649EN-75B
Physical Outline
Unit: mm inch 133.37 0.15 5.251 0.006 (DATUM -A-) 4.00 max 0.157 max
Front side
3.00 typ 0.118 typ (63.67) (2.51)
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 84 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
C 11.43 0.450 36.83 1.450 B 54.61 2.150 A
, , , , , , ,
3.00 0.10 0.118 0.004
1.27 0.10 0.050 0.004
Back side 4.00 0.10 0.157 0.004 2 - 3.00 0.10 2 - 0.118 0.003 85
127.35 0.15 5.014 0.006
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (DATUM -A-)
Detail A 2.50 0.20 0.098 0.008 0.20 0.15 0.010 0.0004 1.27 0.050 Detail B R FULL (DATUM -A-) Detail C 1.00 0.039 168
17.80 0.70
R FULL
3.125 0.125 0.123 0.005
1.00 0.05 0.039 0.002
Note: Tolerance on all dimensions 0.15/0.006 unless otherwise specified.
Preliminary Data Sheet E0012H10 27
3.125 0.125 0.123 0.005
6.35 0.250 2.00 0.10 0.079 0.004
6.35 0.250 4.175 0.164 2.00 0.10 0.079 0.004
34.925 1.375
4.00 min 0.157 min
HB52F648EN/HB52F649EN-75B
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
Preliminary Data Sheet E0012H10 28

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